1. Field of the Invention
The present invention generally relates to an image sensor and a manufacturing method thereof, and more particularly, to a back side illumination (BSI) complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof.
2. Description of the Prior Art
CMOS image sensors (hereinafter abbreviated as CIS) are widely used in various applications such as digital camera. The CIS are used for sensing a volume of exposed light projected towards a semiconductor substrate. To do this, the CIS use an array of pixels, or image sensor elements, to collect photo energy to convert images into electrical signals that can be used in a suitable application. A CIS pixel includes a photodetector such as a photodiode, photogate detector, or phototransistor, to collect photo energy.
One form of CIS, backside-illuminated (BSI) CIS, sense a volume of light projected towards the back side surface of the substrate of the sensor by using pixels located on the front side of the substrate. Please refer to FIG. 1, which is a schematic drawing illustrating a conventional BSI CIS 100. As shown in FIG. 1, the conventional BSI CIS 100 includes a thinned silicon substrate 102 having a plurality of photodiode regions 110. The photodiode regions 110 are electrically isolated from each other by a plurality of shallow trench isolations (STIs) 112. The conventional BSI CIS 100 also includes a plurality of dielectric layers 104a, 104b, 104c and 104d, by which a plurality of metal layers 106a, 106b are respectively sandwiched therebetween, formed on the silicon substrate 102. Said dielectric layers and the metal layers construct the multilevel interconnects as shown in FIG. 1. For simplifying the features of the conventional BSI CIS 100, all the transistor devices are omitted. The conventional BSI CIS 100 is photosensitive to light incident upon the back side 102b of the silicon substrate 102, therefore the conventional BSI CIS 100 further includes a color filter array (CFA) 120 respectively corresponding to the photodiode regions 110 formed on the back side 102b of the silicon substrate 102. And a glass 122 is subsequently formed on the back side 102b of the silicon substrate 102.
The BSI CIS 100 is advantageous in that they provide higher fill factor and reduced destructive interference. However, the silicon substrate 102 must be thin enough that light projected towards the back side 102b of the silicon substrate 102 can reach the pixels. Therefore, a silicon carrier wafer 130 is always in need to provide support for the thinned silicon substrate 102. As shown in FIG. 1, the silicon carrier wafer 130 is bonded to the front side 102a of the silicon substrate 102 before forming the CFA 120. For providing output electrical connection for the BSI CIS 100, a through-silicon via (TSV) 132 is formed to penetrate the silicon carrier wafer 130 and thus expose a bonding pad 108 after forming the CFA 120. Then, a redistribution layer 134, a passivation layer 136, and a solder ball 138 are formed as shown FIG. 1. Additionally, the silicon carrier wafer 130 is sandwiched between the insulating layer 104d and the passivation layer 136 as shown in FIG. 1.
It is noteworthy that the conventional BSI CIS 100 always faces a requirement of low thermal budget due to the CFA 120 formed on the back side 102b of the silicon substrate 100. In detail, while the CFA 120 lowers the thermal budget to 200° C.-250° C., the temperatures for forming the passivation layer 130, the RDL 134, and the solder ball 138 are all higher than 250° C. It is found that the CFA 120 suffers damages after forming the above mentioned elements. Furthermore, the TSV technique, which forms to penetrate the silicon carrier wafer 130, also complicates the process.
Briefly speaking, though the BSI CIS 100 has the advantages of higher fill factor and reduced destructive interference, it still has more problems in process integration and process control. As such, an improved BSI CIS and manufacturing method thereof is desired.